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application note AN250/1188 optimized for high frequency power mos drive a second-generation ic switch mode controller introduction since the introduction of the sg1524 in 1976, inte- grated circuit controllers have played an important role in the rapid development and exploitation of high-efficiency switching power supply technology. the 1524 soon became an industry standard and was widely second-sourced. although this device contained all the basic control elements required for switching regulator design, practical power supplies still required other fun- ctions which had to be implemented with additional external discrete circuitry. an additional development within the semiconduc- tor industry was the introduction of practical power mos which offered the potentialof higher efficiencies at higher speeds with resultant lower overall system costs. in order to be able to take full advantage of the spe- ed capabilities of power mos, it was necessary to provide high peak currents to the gate during turn-on and turn-off to quickly charge and discharge the gate capacitances of 800 to 2000 pf present in hi- gher current units. the development of a second-generationregulating pwm ic, the sg1525a, and its complimentary out- put version, the sg1527a, was a direct result of the desire to add more power supply elements to the control ic, as well as to optimize the interfacing of high current power devices. figure 1 : the sg1524 relating pwm block diagram. this design was the first complete i.c. control chip for switch mode power supplies. 1/13
integrating more power supply functions having achieved the greatest level of acceptance among users of first generation control chips, the 1524 became the starting point for expanding ic controller capabilities. this early device, shown in figure 1, contains a fixed-voltage reference source, an oscillator which generatesboth a clock signal and a linear ramp waveform, a pwm comparator, and a toggle flip-flop with output gating to switch the pwm signal alternately between the two outputs. with this circuitry already defined, a two pronged de- velopment effort was initiated : 1) to add additional features required by most power supply designs and 2) to improve the utility of features already included within the 1524. the resultant block diagram for the sg1525a is shown in figure 2. two general com- ments should be made relative to the overall block diagram. first, in optimizing the output stage for bi- directional, low impedance switching, commitments had to be made as to whether the output should be high or low during the active, or on state. since this is application defined there are needs for both output states, so both were developed with the sg1525a device defined by an output configuration which is high during the on pulse, and the sg1527a confi- gured to remain high during the off state. this dif- ference is implemented by a mask option which eliminates inverterq 4 (see figure 3) for thesg1527a. in all other respects, the 1525a and 1527a are iden- tical and any description of the 1525a characteristics apply equallytothe 1527a.second,a major differen- ce between this new controller and the earlier 1524 is the deletion of the current limit amplifier. there are so many system considerations in providing current control that it is preferable to leave this as a user-de- fined external option and allocate the package pins to other, more universally requested functions. cur- rent limiting possibilities are discussed further under shutdown options. figure 2 : the sg1525a family represents a osecond generationo of ic controllers. application note 2/13
ototem-poleo output stage one of the most significant benefits in using the sg1525a is its output configuration. for the first time it has been recognized in an ic controller that it is more difficult to turn a power switch off than turn it on. with the sg1525a, a high-current, fast transi- tion, low impedance drive is provided for both turn- on and turn-off of an external power transistor or power mos. the circuit schematic of one of the two output stages contained within the device is shown in figure 3. this is a two-state output, eitherq 8 is on, forming a low saturation voltage pull-down, or q 7 is on, pulling the output up to v c .notethatv c is a se- parate terminal from the v i supply to the rest of the device. this offers the benefits of potentially operating the output drive from a lower supply than the rest of the circuit for power efficiencies, decoupling of drive transients from more sensitive circuits, and a third terminal for extracting a drive signal. note that even though v c can be set either higher or lower than v i , the output cannot rise higher than approximately 1 1/2 volts below v i . figure 3 : one of two power output stages con- tained within the sg1525a which con- duct alternately due to the internal flip- during the transition between states, there is a slight conduction overlap between source and sink which results in a pulse of current flowing from v c to ground. however, due to the high-speed design configurationof this stage, this current spike lasts for only about 100ns. a typical current waveform at v c is shown in figure 4. this transient will normally be decoupledfrom the rest of the control power by a 0.1 m f capacitor from v c to ground but it should not, otherwise, cause a problem unless very high fre- quency operation is contemplated where it will con- tribute to overall device power dissipation, by becoming a significant portion of the totalduty cycle. the output saturation characteristics of this stage are shown in figure 5. the source transistor, q 7 is a straight forward darlington and its saturation voltage remains between 1 and 2 v out to 400 ma under the assumption that v i v cc . the sink transistor, q 8 , however, has a non-uniform characteristic which needs explanation. at low sink currents, the 1 ma current source through q 5 insures a very low satu- ration voltage at the output. as load current increa- ses past 50 ma, q 8 beginsto come out of saturation for lack of base drive but only up to about 2 v. here diode d 2 becomes forward biased shunting a por- tion of the load current through q 5 to boost the base current into q 8 . with this circuit, the sink transistor can both support high peak discharge currents from a capacitive load, as well as insure the low static hold-off voltage required for bipolar transistors. a typical output configuration for a push-pull bipolar transistorpower stage is shown in fig. 6. with a stea- dy state basedrive current from thesg1525aof 100 ma, this stage should be able to switch 1 to 5 a of transformer primary current, depending upon the choice of transistors. the sum of r 1 and r 2 deter- mine the maximum steady state output current of the sg1525a while their ratio defines the voltage figure 4 : current ospikingo on the v c terminal caused by conduction overlap between source and sink is minimized by high- speed design techniques. application note 3/13
figure 5 : the output saturation characteristics of the sg1525a provide both high drive current an low hold-off voltage. across c 2 which, at turn off, becomes the reverse v be for q 1 . with the values given, the output current and voltage waveforms are shown in figure 7 for a one microsecond pulse. if power mos are used for the output switches as shown in figure 8, the inter- facing circuitry can become even simpler with only a small series gate resistor potentially required to damp spurious oscillations within the power device. push-pulldirect transformer drive is also particularly advantageouswith sg1525a as shown in figure 9. figure 6 : a typical push-pull converter power stage using external bipolar power transistor switches figure 7 : base current waveforms (figure 6 circuit) show the enhanced turn-on and turn-off current possible with the sg1525a. a version of this configuration is required for isola- tion when the control circuit is referenced to the se- condary side of an off-line power system, and to provide level shifting of drive signals for bridge and full bridge switching. the configuration of figure 9 has a couple of important advantages.first, by con- necting the drive transformer primary directly be- tween the outputs of the sg1525a, no center-tap is needed and the full primary is driven with opposite polarities. secondly, between each output pulse, both outputs are pulled to ground which effectively shorts the two ends of the primary winding together coupling a low-impedance turn-off signal to the swit- ching transistors. a useful single-ended configuration, typical of buck regulators, is shown in figure 10. here the sg1525a outputs are grounded and the pwm signal is taken from the v c terminal which switches close to ground during each clock period as the internal source tran- sistors are alternately sequenced. application note 4/13
figure 8 : replacing bipolar transistors with power mos provides even greater simplicity due to the low driving impedances of the sg1525a in each transition. figure 9 : the sg1525a is ideally suited for driving a low-power base drive transformer and eliminates the need for a primary center- tap. figure 10 : a single-ended ground-referenced power stage for a flyback or boost regulator. controlling power supply start-up although the advantages of the sg1525a's output stage will often be reason enough for its selection, there are several other important and useful features incorporated within this product. one problem pre- viously overlooked in pwm circuits is keeping the output under control as the supply voltage is turned on and off. undefined states, particularly the possi- bility of turning on an output before the oscillator is running,can be quiteawkward, if notcatastrophic.to prevent this, the sg1525a has incorporated an un- der-voltage lockout circuit which effectively clamps the outputs to the off state with as little as 2 1/2 v of supply voltage which is less than the vol-tage requi- red to turn the outputs on. this clamp is maintained until the supply reaches approximately 8 v insuring that all the remaining sg1525a circuitry is fully ope- rational prior to enabling the outputs. the clamp re- activates when the supply is lowered to approximately 7.5 v. there is about 500 mv of hy- steresis built in to eliminate clamp oscillation at thre- shold. application note 5/13
anotherimportant aspect of power sequencingis re- strainingthe outputsfrom immediately commanding a 100 % duty cycle when they are activated. this is accomplished by a slow turn on (soft-start) which is defined by an internal 50 m a current source in con- junction with an externally applied capacitor. the details of this power sequencing system are shown in figure 11. q 3 and q 4 are the output gatesnormally driven by the oscillator thr ough d 2 to provide output blanking be- tween pulses. (one of these transistors is shown as q 2 in figure 3). at low supply voltages, q 2 conducts with base drive from the 20 m a current source. q 2 pro- vides three functions.first, current through r 4 activa- tes the output gates with minimum voltage drop. second, current through r 5 activates the shutdown transistor q 5 holding the soft-start capacitor, c ss ,di- scharged.third, r 2 provides a small bucking voltage across r 3 for hysteresis at the switch point. when the input voltage becomes high enough to provide a little more than one volt at the base of q 1 , that transistor turns on. this turns off q 2 , activating the outputsand allowing c ss to begin to chargefrom the internal 50 m a current source. the time to reach approximately 50 % duty cycle will be t= ( 2volts ) c ss 50 m a figure 11 : the internal power turn-on, soft-start, and shutdown circuitry of the sg1525a. power supply shutdown an important part of any pwm controller is the ability to shut it down at any time for a variety of reasons, including system sequencing requirements or fault protection.several options are available to the user of the sg1525a, which require an understanding of the capability of the shutdown terminal, pin 10. re- ferring to figure 11, the base of q 5 is turned on by a signal which is clamped to approximately 1.4 v by the actionof d 1 and the v be ofgatesq 3 andq 4 . this holds the outputs off and keeps c ss discharged by q 5 which, with r 9 , becomes a 100 m a net current sink. if, during normal operation, pin 10 is pulled high, three things happen.first, the outputs are turned off within 200 ns through d 1 . second, the pwm latch is set by q 6 so that even if the signal at pin 10 were to disappear, the outputs would stay off for the du- ration of that period, being reset by the next clock pulse. third, q 5 is activated commencing a 100 m a application note 6/13
dischargeof c ss . however, if the activation pulse on pin 10 has a duration shorter than 1/3 of the clock period, the voltage on c ss will remain high and soft- start will not be reactivated. naturally, a fixed signal on pin 10 will eventually discharge c ss , recycling soft-start. thus, the shutdown pin provides both sequencing capability as well as a convenient port for protective functions, including pulse-by-pulse current limiting. regulating pwm performance improvements the sg1525a also offers significant performance and application improvements in almost all of the additional basic functions of a pwm over those ob- tainable with earlier devices. a general description of these features is outlined below : reference regulator the output voltage of this regulator is internally trim- med to 5.1 v 1 % during manufacture,eliminating the need for adjusting potentiometersin most applica- tions. error amplifier sg1525a uses the same basic transconductance amplifier as the sg1524 with an important differen- ce : it is powered by v i rather than v ref . now the in- put common-mode range includes v ref eliminating the need for a voltage divider with its attendant to- lerances. an additional feature relative to the error amplifier is that the shutdown circuitry feeds into a separateinput to the pwm comparator allowing pul- se termination without affecting the output of the er- ror amplifier which might have a slow recovery, depending upon the external compensation net- work selected. an important benefit of a transcon- ductance amplifier is the ease with which its current mode output can be over-ridden by other external controlling signals. pwm comparator the significant benefit of the sg1525a'spwm com- parator is in its following latch. a common problem with earlier devices was that any noise or ringing on the output of the error amplifier would affect multiple crossings of the oscillator ramp signal resulting in multiple pulsing at the comparator's output. the sg1525a's latch terminates the output pulse with the first signal from the comparator, insuring that there can be only a single pulse per period, remo- ving all jitter or threshold oscillation from the system. another important advantageof this latch is the abi- lity to easily implement digital or pulse-by-pulse cur- rent limiting by merely momenetarily activating the shutdown circuitry within the sg1525a. this could be as simple as connecting pin 10 to a ground-ref- erenced current sensing resistor. for greater accu- racy, some added gain may be advantageous. once a current signal causes shutdown, the output will remain terminated for the duration of the period, even thoughthe current signalis now gone.an oscil- lator clock signal resets the latch to start each period anew. oscillator the functions of the oscillator within the sg1525a have been broadened in two important aspects. one is the addition of a synchronizationterminal, pin 3, allowing much easier interfacing to an external clock signal or to synchronize multiple sg1525a's together. the other is the separation of the oscilla- tor's discharge network from its charging current source for deadtime control. reference should be made to the schematic of figure 12 for an under- standing of the operation of this circuit. the heart of this oscillator is a double-thresholdcomparator, q 7 and q 8 , which allows the timing capacitor to charge to an upper threshold by means of the current sour- ce defined by r t and mirrored by q 1 and q 2 . the comparator then switches to a lower threshold by turning on q 10 and discharges c t through q 3 and q 4 with a rate defined by r d . as long as c t is di- scharging, the clock output is high, blanking the out- puts. since the overall oscillator frequency is defined by the sum of the charge and discharge times, there are three elements now in the frequency equation which is approximately : f 1 c t (.07 r t +3r d ) external synchronization can easily be accompli- shed with a 2.8 v positive pulse at pin 3. this will turn on q 9 , lowering the comparator threshold below wherever the voltage on c t may happen to be. two factors should be considered : first, the voltage on c t determines the amplitude of the pwm ramp, and if the sync occurs too early, the loop gain will be hi- gher and the resolution may be worse. second, the sync circuit is regenerative within 200 ns ; and, while a wider pulse can be used,c t will notbegin torechar- ge as long as the sync pin is high. for synchronizing multiple sg1525a devices together, one need only to define a master with the correct r t c t time con- stant, connect its output pin to the slave sync pins, and set each slave r t c t for a time constant 10-20 % longer than the master. application note 7/13
figure 12 : a simplified schematic of the sg1525a's oscillator circuitry. figure 13 : 200 w, off-line forward converter. application note 8/13
a 200 watt, off-line, forward con- verter the ease of interfacing the sg1525ainto a practical power supply system can be illustrated by the off- line, power converter shown in figure 13. this 200 w supply places the control circuitry on the primary side of the power transformer where direct coupling can be used to drive the power switch. while sim- plifying the drive electronics, this configuration usually requires an isolated voltage feedback signal which is most easily accomplished by an optocou- pler driven by some type of voltage regulatoric such as a l123 or lm723. one other undefined block in figure 13 is the auxiliary power supply which sup- plies the low voltage, low current bias supply for the sg1525aand the drive for q 1 the powerswitch. the choice of the sgsp479 power mos for this switch keeps the total power requirements from the auxi- liary supply at less than 1 w ; readily implemented with a small, line-driven transformer. this converter is designed to operate at 150 khz which is accomplished by running the sg1525a at 300 khz and using only one of the outputs.this also automatically insures that the duty cycle can never be greater than 50 %, a requirement of the power tran- sformer in this configuration. the high operating fre- quency allows the output filter's roll-off to be set at 12 khz, greatly simplifying the overall loop stability con- siderations as adequate response can be achieved with only the single-pole compensation of the error amplifier provided by the 0.05 m f capacitor on pin 9. the totem-pole output of the sg1525a is used to ad- vantage to drive q 1 by providing a 400 ma peak cur- rent to charge and discharge the power mos gate capacitance while keeping overall power dissipation low. waveform photographs of this operation are shown in figure 14. figure 14 : current and voltage waveforms for the 200 w off-line forward converter with a sg1525a direct driven power mos switch (operating frequency is 150 khz with output current equal to 40 a). application note 9/13
when operatingat full load, the efficiency of thiscon- verter is 73 % with by far the greatest power losses occurring in the output rectifiers-even though schottky devices have been selected. switching losses have been minimized by the fast current transitions, primarily defined by the leakage inductance of the transformer. although this swit- ching time could probably be even further reduced, there could be problems with current spikes during rise time due to schottky rectifier capacitance. current limiting for this converter is provided by measuring the current in sgsp479 with the 0.1 w resistor in series with the source and using this voltage to activate the shutdown circuitry within the sg1525a. while this will provide a fast-acting short circuit protection on a pulse-by-pulse basis, a comparator may need to be added for a more accu- rate current limit threshold. figure 15 : 500 w, 100 khz half-bridge schematic. application note 10/13
transformer winding data 500 w, 100 khz, off-line, half-bridge converter : t1 core : ferrox 486t250-3c8 pri : 14 t #22awg sec (2) : 7 t #22awg t2 core : ferrox ec52-3c8 (ee) pri : 14 t, 2 layers, 2 #16awg in parallel sec (2) : each 2 t, c.t., copper strap 0.01o x 0.8o t3 core : ferrox 486t250-3c8 pri : 1 t sec : 20 t, c.t. #22awg t4 117 v/220 v, 25 v, 0.15 a, 50-60 hz l1 core : ferrox if30-3c8 4 turns, 5 #12awg in parallel 500 watt, off-line, half-bridge converter the circuit shown in figure 15 uses a pair of sgsp479 power mos in a half-bridge configuration with the sg1525a chip referenced to the secondary side of the power transformer. the power mos gates are driven directly from the control chip output through step down and isolation transformer t1. the sg1525a output terminals (pins 11 and 14) provide active pull-up and pull- down (dual source/sink for the primary of t1. this provides the fast, high current turn-on and turn-off pulses needed for the power mos gates. in addi- tion, the two ends of the primary windings are shor- ted to ground during deadtime, which prevents accidental turn-on by transients. note that the cur- rent supplied by the sg1525a outputs drops to a small value when the gate capacitance has been charged or discharged to the desired gate voltage. damping resistors with series blocking capacitors across the two secondaries of t1 minimize ringing due to the power mos gate capacitance and the in- ductance of t1 and lead inductance, particularly du- ring deadtime. deadtime for the sg1525a is set very simply by a single resistor between pins 5 and 7. only a small amountof deadtime isneededsince the power mos have no storage time and a very short delay time. slow turn-on is accomplished by a single capacitor at pin 8. current limiting is provided by current transformer t3 in series with the primary of the power transfor- mer t2. the signal is rectified, threshold adjusted and sent to the shutdown terminal, pin 10, of the sg1525a. waveforms of the converter are shown in the scope photos of figure 16. current rise and fall times are 20 ns and 10 ns. figure 16 : performance waveforms for the half- bridge, 500 w, 100 khz converter with output current of 80 a. application note 11/13
improved performance ; less complexity althoughpower supply designersfor some time now have had an ever widening inventory of ic compo- nents available to ease their design tasks, the final measure of improvement has to be in terms of sy- stem performance versus cost. with fewer interface components to the power stages, freedom from po- tentiometer adjustments, protected start-up and shut-down, a built in soft-start network and several additional system-level features, the sg1525a pro- vides a significant contribution to both performance and costs while simultaneously making the designe- r's task easier. with these accomplishments, it is clear thatthis device truly doesrepresenta step-fun- ction improvement, introducing a second-genera- tion of power control components. ? 1984 by unitrode corporation. all rights reserved. this bulletin, or any part or parts thereof, must not be reproduced in any form without permission of the copyright owner. application note 12/13
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics printed in italy all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the nether- lands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. application note 13/13

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